FPGA Implementation of a Novel Efficient Vedic FFT/IFFT Processor For OFDM

ABSTRACT: Several new generation wideband data communication systems nowadays, have adopted Orthogonal Frequency division Multiplexing technique. FFT/IFFT is one of the main kernel in the OFDM system, therefore, special attention needs to be given to optimize the FFT block. Hence, utilizing low power, area efficient as well as high speed multipliers and adders in Fast Fourier Transform will ensure enhanced performance and efficiency. Urdhva Tiryakbhyam is one of the age-old Indian Vedic sutra dealing with multiplication which enables parallel generation of partial products and completely eliminates unwanted multiplication steps. Multipliers implemented using Vedic mathematics are superior in terms of area efficiency. Carry Select Adders (CSLA) are one of the fastest adders used in several processors to perform fast and complex arithmetic functions. In this work, the vedic multiplier which is developed using the Urdhva Tiryakbayam Sutra along with modified carry select adder is used to perform a Radix-2 pipeline Fast Fourier Transform. The Fast Fourier Transform (FFT) which is implemented using vedic multiplier and modified adder is then compared with FFT implemented using traditional multipliers and adders and its performance is verified. Such an FFT will be most suitable to OFDM communication system. The coding of the FFT processor developed based on vedic mathematics is done in VHDL (very high speed integrated circuit hardware description language) and synthesis is done using Xilinx ISE series.